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fpga-verification 1.0.0

This is a breaking release of the simulation API.

Version 1.0.0 and later are licensed under the Reciprocal Public License 1.5 (RPL-1.5). Licensing of earlier published releases is unchanged.

Breaking changes

  • Removed BaseVIPPredictor. IP-specific register, functional, and temporal semantics now live in custom scoreboards and behavior models.
  • Reworked BaseVIPScoreboard into a strict ordered protocol engine with input, control, and reset hooks.
  • Replaced implicit unchecked expectations with explicit CheckMode.EXACT and CheckMode.SHAPE contracts.
  • Added explicit UserPacketPolicy.DROP and UserPacketPolicy.PASSTHROUGH; DROP is the default.
  • Added reset watching with pending-work abort and sticky mismatch behavior, plus drain() with a configurable quiet output window.
  • Added the FrameSource/FrameTransaction contract for non-VIP physical sources feeding output-only VIP paths.

Configuration

Generated component tests now use ComponentConfig and hdl_parameter(). run_intel_component_test() passes the same resolved configuration used for Platform Designer generation to cocotb as strict JSON through extra_env. Cocotb tests restore it with load_runtime_config(); missing, extra, malformed, or incorrectly typed fields fail immediately.

Named host configurations may be selected with FPGA_VERIFICATION_CONFIG_CASE. The resolved runtime JSON remains the only configuration visible to cocotb.

Migration guidance

Projects using the earlier predictor API should move IP-specific calculation and state into their own functional and behavior models. A custom scoreboard adapts observed protocol objects to those models and queues explicit output expectations for BaseVIPScoreboard.

The framework codecs, agents, and scoreboard continue to support parallel pixels. Project-specific supported configurations remain the responsibility of each downstream verification environment.